1. Field of the Invention
This invention relates to integrated circuit design and more specifically to computer aided design layout and ensuring compliance with layer-density rules in a design layout in preparation for fabrication.
2. Description of the Relevant Art
Design of an electronic circuit, for example, an integrated circuit (IC), is a complicated and time-consuming process. FIG. 1 illustrates a typical design flow of an integrated circuit device from conception through the generation of a fabrication ready design layout. Generally, the design flow commences with defining the design specifications or requirements, such as required functionality and timing, as indicated at 110. The requirements of the design are implemented, for example, as a net-list or electronic circuit description, as indicated at 120. The implementation can be performed by, for example, schematic capture (drawing the design with a computer aided design tool) or more typically, utilizing a high-level description language such as VHDL, Verilog and the like. The implemented design may be simulated to verify design accuracy, as indicated at 130. Design implementation and simulation may be iterative processes. For example, errors found by simulation may be corrected by design implementation and re-simulated.
Once the design is verified for accuracy through simulation, a design layout is created, as indicated at 140. The design layout may describe the detailed design geometries and the relative positioning of each design layer to be used in actual fabrication of the electronic circuit and is typically implemented as one or more design files encoding representations of the layers and geometries. The design layout is typically very tightly linked to overall circuit performance (area, speed and power dissipation) because the physical structure defined by the design layout determines, for example, the transconductances of the transistors, the parasitic capacitances and resistances of the circuit, and the silicon area used to realize a certain function. The detailed design layout may require a very intensive and time-consuming design effort and is typically performed utilizing specialized computer aided design (CAD) or Electronic Design Automation (EDA) tools.
During creation of the design layout, a place and route tool is often used to place geometries on various layers of the design layout and to connect or route the cells together. In modern semiconductor design technologies, many metal layers are used to implement interconnections throughout an integrated circuit. For some integrated circuits, one or more polysilicon (poly) layers, or even active areas, are also used to implement interconnections.
Once the design layout is created, it is checked against a set of design rules in a design rule check (DRC) operation, as indicated at 150. The created design layout typically must conform to a complex set of design rules in order, for example, to ensure a lower probability of fabrication defects. The design rules specify, for example, how far apart various geometries on different layers must be, or how large or small various aspects of the layout must be for successful fabrication, given the tolerances and other limitations of the fabrication process. Design rules are typically closely associated with the technology, fabrication process and design characteristics. For example, different minimum spacing amounts between geometries may be specified for different sizes of geometries, and a minimum or maximum density of a design layer for a given sized area may be specified. DRC may be a time-consuming, iterative process that often requires manual manipulation and interaction by the designer. The designer may perform design layout and DRC iteratively, reshaping and moving design geometries to correct all layout errors and achieve a DRC-clean (violation-free) design.
Circuit extraction is performed after the design layout is completed and error free, as illustrated at 160. The extracted circuit may identify individual transistors and interconnections, for example, on various layers, as well as the parasitic resistances and capacitances present between the layers. A layout versus schematic check (LVS) may be performed, as indicated at 170, in which the extracted net-list is compared to the design implementation created at 120. LVS may ensure that the design layout is a correct realization of the intended circuit topology. Any errors such as unintended connections between transistors, or missing connections/devices, etc., may be corrected in the design layout before proceeding to post-layout simulation, as indicated at 180. The post-layout simulation may be performed using the extracted net-list, which may provide an assessment of the circuit speed, the influence of circuit parasitics (such as parasitic capacitances and resistances), and any glitches that may occur due to signal delay mismatches. Once post-layout simulation is complete and errors found by LVS are corrected, the design may be ready for fabrication and may be sent to a fabrication facility
As electronic circuit densities increase and technology advances, for example, in deep sub-micron circuits, skilled designers attempt to maximize the utilization of the design layout area and the manufacturability and reliability of the circuit. For example, to increase planarity in anticipation of chemical mechanical polishing of the metal layers while processing a wafer, open areas that exceed certain sizes may be filled with dummy metal beforehand, during chip design. A traditional metal fill tool uses a “flood fill” to fill the open areas with additional metal.
Deep sub-micron designs typically have stringent design rules that are often not recognized or not properly handled by existing EDA tools. Therefore, when creating a design layout at 140, for example, design rule violations may be created that must be corrected. For example, a tool that is used to flood fill a given area of the design with metal on a particular metal layer (e.g., in order to attempt to meet a layer density rule) may introduce other errors.
Because EDA tools are increasingly relied upon to create design layouts, and because conventional EDA tools do not prevent the creation of certain violations, thousands of violations can be created that must be corrected. Performing a DRC and manipulation of the design layout to correct these violations often requires manual interaction from the designer. Creation of a violation-free design layout becomes a critical, time-consuming process. Due to the complexity of the design and because the layout design flow can be repeated throughout the design process, manually fixing violations may not be an affordable approach.